clock test
英 [klɒk test]
美 [klɑːk test]
网络 时钟测试
双语例句
- For example, you might want a system clock to always return the same time so that your test has repeatable results that you can verify.
例如，您可能希望系统时钟总是返回相同的时间以便测试能够有可验证的重复结果。 - THE CLOCK TEST: If you feel like he or she` s been watching you, suddenly look at the clock then quickly look at him/ her.
时钟测试：要是你感到他/她在看你，那就试试突然抬头看钟然后又转头看他/她。 - "We've been working around the clock on test methods for the virus," Shu Yuelong, director of the Chinese National Influenza Center, told Xinhua.
“我们已经在夜以继日的研究测试病毒的方法”中国国家流感中心的书越龙告诉新华社说。 - With better measurements of mutation rates, we could improve the calibration of the evolutionary clock, or test ways to reduce mutations, for example.
如果能够更好的掌握测量突变速率，我们将能够改善进化时钟的标准，或者测试一些方法减少突变。 - Clock test system for electric energy measuring devices based on GPS
基于GPS的电能计量装置时钟测试系统 - In this part, we focus on the signal-dealing circuit design such as clock circuit, AD circuit, zero-calibration and compensation circuit and numeric integral circuit. 2. Test system of MIMU.
包括了时钟电路、AD采样电路、微惯性器件的校零和补偿电路、数字积分电路和串口输出电路：2、计算机测试系统的设计。 - The technology of Phase Locked Loop is used to realize synchronization of clock pulse and the test voltage's frequency in order to ensure the measurement of veracity of φ.
另采用锁相环技术实现时钟脉冲与试验电压频率同步，以保证长时间测量时φ值的准确性。 - Clock Drawing Test and Clock Drawing Test in ADHD Children
钟面画测试及其在ADHD儿童中的研究 - New Architecture of Accurate Clock Generator in IC Test System
IC测试系统精密定时器的新结构 - Some date have been obtained about long-term and short-term shifting rate of clock frequency based on investigating and tracing test on S-1240 SPC exchanges. And gives reference evidences of maintenance period of clock frequency of SPC exchanges.
在调研以及跟踪S－1240程控交换机时钟频率的测试基础上得出有关时钟频率短期和长期频率偏移的数据，提出了我国电信网中程控交换局时钟频率的维护周期的参考依据。 - The authors introduce the structure of cuneiform light system in aircraft clock, and also offer some measures and test results for improving the technique index of light system.
本文介绍了航空钟钟内楔形照明系统的结构，提高红光照明各项技术指标采取的措施及测量结果。 - Design of random clock error test bench in verilog
基于Verilog的随机时钟误差测试平台设计 - Introduces the synchronous clock network's mode and the application in the SDH radio circuit, presents the practical performance test methods
介绍了同步时钟组网的方式和在SDH微波电路中的实际应用，以及同步时钟的测试方法 - Clock Synchronization of the Networked Test System
网络化测试系统的时钟同步 - A method to design a random clock error test bench in verilog was introduced which combines the simulating verification of the video mode detector.
结合视频模式识别模块的仿真验证，介绍了一种基于Verilog的随机时钟误差测试平台的设计方法。 - A Discussing of Clock Generating Technique in High Speed Error Test Set
高速误码测试仪中时钟产生技术讨论 - In the Windows 9x, implementation of the real-time clock hardware interrupt is illustrated by the source code analysis about real-time clock interrupt VxD and its test program.
通过对实时钟中断的虚拟设备驱动程序源代码及测试程序源代码的分析，说明了实时钟硬件中断在Windows9x环境下的实现过程。 - This article introduce the principle of Digital Signal Processor, specially refer to basic concept and design technique, include: instruction set, pipeline, memory organization, hardware interface, adder, multiplier, clock strategy, test technique.
阐述了数字信号处理器的原理，重点介绍了设计数字信号处理器芯片的简单概念及设计方法，包括指令集、流水线、存储器组织、硬件接口、加法器、乘法器、时钟方案、测试接口等等。 - Clock drawing test is used widely to study and test the cognitive deficits and the cognitive decline in old population and proved to be a useful screening tool for dementia patient.
钟面画测试被广泛用于研究和测试老年人群中的各种认知缺陷和认知老化，是一种有用的筛选老年痴呆症病人的工具。 - In mixed-mode BIST low power test scheme, the gating of system clock scheme is applied to achieve pseudo-random low power test, and utilize the characteristic of the folding sequences at the phase of deterministic test to gain low power dissipation test.
2提出了一种混合BIST低功耗测试方案：根据混合BIST测试方案的特点，利用门控时钟测试方法实现了混合BIST中伪随机低功耗测试； - Methods 193 normal subjects were tested by mini-mental state examination ( MMSE), word immediate recall and word delayed recall test, clock drawing test, digit span test and verbal fluency test.
方法：对193名正常老年人采用简明智力状态检查（MMSE）、词语即刻回忆和延迟回忆、画钟表、数字广度和词语流畅性测验等神经心理学测验进行认知测评。 - After the introduction of the clock reference indicators, detailed analyses of the trial system clock input and clock processing circuit, as well as the test results of the clock performance in the trial system are provided.
通过时钟特性指标的介绍，本文详细分析了试验系统的时钟输入和沿路的时钟处理电路，测试了试验系统的时钟性能。 - Finally, I have carried on the test to the HDMI output card, has carried on the analysis to the test result, and proposed a solution method for clock jitter according to the test result.
最后，对HDMI输出卡进行了测试，对测试结果进行分析，并根据测试结果提出了对时钟抖动问题的解决办法。 - Finally, based on the realization of the above systems, we built a clock synchronization test platform of networked control system based on ICE. The communication system has been tested clock synchronization to verify its capability.
最后，在实现上述系统的基础上，构建了基于ICE的网络化控制系统的时钟同步测试平台，并对系统进行了时钟同步测试，从而检验了网络通信平台的工作能力。 - If supply voltage or clock frequency is reduced, time for test will be increased, and a number of faults which only appears in high-frequency test will be detected difficultly.
如果为了降低功耗而减少供电电压或时钟频率，又会增加测试时间，影响测试效率，并会使得一些在高频测试下才能显现的故障难以被测出。 - The clock generator can be used for arbitrary waveform generators, oscilloscopes, logic analyzers and other digital test instruments.
这套宽带高精度可变时钟发生器的产生方案可用于任意波形发生器、示波器、逻辑分析仪等数字化测试仪器中。 - Then the clock jitter measurement results using simple correlated sampling, complex correlated sampling, SNR method and parameter estimation method, are presented with the performance of trigger clock. Finally, the photographs of these test system are given.
然后给出简单相干采样法、信噪比测量法、参数估计法测量时钟抖动的测量结果以及触发时钟的性能，最后给出各个测试系统的实物照片。 - First it analyzes the phase rotation and inter-carrier interference of the OFDM sub-carriers caused by the clock frequency deviation, and carries on a deviation test for the trial system which verifies the conclusions of theoretical derivation.
首先分析了时钟频率偏差对OFDM子载波造成的相位旋转和载波间干扰，并针对试验系统进行偏差测试，验证了理论推导的结论。 - Theoretical analysis and simulation of RF power measurement, channel design, and clock synthesis, and draw the schematic and PCB. Finally, test the designed circuit.
理论分析和仿真了射频大功率测量、通道设计和时钟合成，绘制了原理图和PCB。最后，测试所设计的硬件电路。